module clockWithInput1(clk, rst, o1, o2, o3, o4, o5, o6, aE, enable, position, in);
//----------------------------------------------------------------------------------------
input clk;// (Key 3)
input rst;// (SW 17)
input [2:0]position;// position of each display signal, made up of three switches(SW 14, SW 13, SW12---->0..0..0)
input enable;// enable for each position(SW15)
input aE;// enabler for the algorithim (SW 16)
input [3:0]in;// value assigned to each position
//-----------------------------------------------------------------------------------------
output [6:0]o1;// outputs for HEX display(HEX 3)
output [6:0]o2;//(HEX 2)
output [6:0]o3;//(HEX1)
output [6:0]o4;//(HEX 0)
output [6:0]o5;//(HEX 4)
output [6:0]o6;//(HEX 5)
//-----------------------------------------------------------------------------------------
reg [6:0]o1;// input/ algorithim HEX display
reg [6:0]o2;
reg [6:0]o3;
reg [6:0]o4;
//-----------------------------------------------------------------------------------------
reg [6:0]o5;// counter timer HEX display
reg [6:0]o6;
//-----------------------------------------------------------------------------------------
reg [2:0] state;// declaring stat parameters
reg [2:0] nextState;

parameter start  =3'd0;
parameter a_b = 3'd1;
parameter b_c = 3'd2;
parameter c_d = 3'd3;
parameter finish = 3'd4;
//-----------------------------------------------------------------------------------------
reg [1:0] countAlg;// count used for finished state
//-----------------------------------------------------------------------------------------
reg [3:0] outA;// register optputs used for algorithim
reg [3:0] outB;
reg [3:0] outC;
reg [3:0] outD;
//-----------------------------------------------------------------------------------------
reg [3:0]out1;// register outputs used for initializing input values 
reg [3:0]out2;
reg [3:0]out3;
reg [3:0]out4;
//-----------------------------------------------------------------------------------------
reg [5:0]count; // counter used for seconds
reg [31:0]timer;// current clock time
reg [31:0]timerMax;// maxed timer input
//-----------------------------------------------------------------------------------------
always @ (posedge clk)// input statment
begin 
	if (rst == 1'b1)
		begin 
			out1 <= 4'd0;
			out2 <= 4'd0;
			out3 <= 4'd0;
			out4 <= 4'd0;
					end
	else 
		begin
			case (position)
				3'd0: begin
							if (enable == 1'b1)
								begin
									out1 <= in;
								end
							else
								begin
									out1 <= out1;
								end
							end
							
					3'd1: begin
							if (enable == 1'b1)
								begin
									out2 <= in;
								end
							else
								begin
									out2 <= out2;
								end
							end
							
						3'd2: begin
									if (enable == 1'b1)
										begin
											out3 <= in;
										end
									else
										begin
											out3 <= out3;
										end
									end
						3'd3:  begin
									if (enable == 1'b1)
										begin
											out4 <= in;
										end
									else
										begin
											out4 <= out4;
										end
									end
						endcase
					end
				end
						
						
//-----------------------------------------------------------------------------------------
always @ (posedge clk) // update next state
	begin
	timerMax = 32'd50000000;  
		if (rst == 1'b1)				 
			begin 
				timer <= 1'b0;
				count <= 1'b0;
				state <= start;// resets state
			end
		else 
			begin 
				timer = timer + 1'b1;// adds one value to the timer for each clock cycle
				if ( timer == timerMax)// determines if the timer has gone through [5*(10^7)] cycles
					begin// state update within timer always
						if (rst == 1'b1)
							begin
								if (aE == 1'b1)// enable signal must be within the state update to mandate algorithim use
									begin
										state <= start;
									end
								else
									begin
										state <= state;
									end
							end
						else
							begin
								if (aE == 1'b1)
									begin
										state <= nextState;
									end
								else
									begin
										state <= state;
									end
								count <= count + 1'b1;// after one second, the counter is raised by one
								timer <= 1'b0;
							end
					end
				else 
					begin 
						count <= count;
					end 
			end
	end
//------------------------------------------------------------------------------------------
always @ (*)// calculate next state
	begin

		case(state)
	 
			start:begin// state Start
							nextState = a_b;
					end
			 
			a_b:	begin// state position A to B
							nextState = b_c;
					end

				
			b_c:	begin// state position B to C
							nextState = c_d;
					end
				
			c_d:	begin// state position C to D
						nextState = finish;
					end
				
			finish:	begin// state Finish
							countAlg = countAlg + 1'b1;
								if(countAlg < 4'd4)
									begin
										nextState = a_b;
									end
								else
									begin
										nextState = finish;
									end								// find a way to end the machine after the finish loop is compleated
						end
			endcase		
	end
//----------------------------------------------------------------------------------------****
always @ (posedge clk)// state logic
	begin
		case(state)
			start: begin// state Start
					outA <= out1;
					outB <= out2;
					outC <= out3;
					outD <= out4;
			end
			
			a_b:	begin// state position A to B
					if(outA < outB)
					begin
						outA <= outB;
						outB <= outA;
					end
				else
				begin
					outA <= outA;
					outB <= outB;
				end
			end

			b_c:  begin// state position B to C
						if(outB < outC)
							begin
								outB <= outC;
								outC <= outB;
							end
						else
							begin
								outB <= outB;
								outC <= outC;
							end
					end

			c_d: begin// state position C to D
					if(outC < outD)
						begin
							outC <= outD;
							outD <= outC;
						end
					else
						begin
							outC <= outC;
							outD <= outD;
						end
					end
			//maybe put state final as the last case in the statement			
			endcase
	end
//-----------------------------------------------------------------------------------------------------
always @ (posedge clk)
	begin 
		case(outD) 
				4'h0: o1 = 7'b1000000;
				4'h1: o1 = 7'b1111001;
				4'h2: o1 = 7'b0100100;
				4'h3: o1 = 7'b0110000;
				4'h4: o1 = 7'b0011001;
				4'h5: o1 = 7'b0010010;
				4'h6: o1 = 7'b0000010;
				4'h7: o1 = 7'b1111000;
				4'h8: o1 = 7'b0000000;
				4'h9: o1 = 7'b0011000;
				4'hA: o1 = 7'b0001000;
				4'hB: o1 = 7'b0000011;
				4'hC: o1 = 7'b1000110;
				4'hD: o1 = 7'b0100001;
				4'hE: o1 = 7'b0000110;
				4'hF: o1 = 7'b0001110;
		endcase
		
		case(outC) 
				4'h0: o2 = 7'b1000000;
				4'h1: o2 = 7'b1111001;
				4'h2: o2 = 7'b0100100;
				4'h3: o2 = 7'b0110000;
				4'h4: o2 = 7'b0011001;
				4'h5: o2 = 7'b0010010;
				4'h6: o2 = 7'b0000010;
				4'h7: o2 = 7'b1111000;
				4'h8: o2 = 7'b0000000;
				4'h9: o2 = 7'b0011000;
				4'hA: o2 = 7'b0001000;
				4'hB: o2 = 7'b0000011;
				4'hC: o2 = 7'b1000110;
				4'hD: o2 = 7'b0100001;
				4'hE: o2 = 7'b0000110;
				4'hF: o2 = 7'b0001110;
		endcase
	
	case(outB) 
				4'h0: o3 = 7'b1000000;
				4'h1: o3 = 7'b1111001;
				4'h2: o3 = 7'b0100100;
				4'h3: o3 = 7'b0110000;
				4'h4: o3 = 7'b0011001;
				4'h5: o3 = 7'b0010010;
				4'h6: o3 = 7'b0000010;
				4'h7: o3 = 7'b1111000;
				4'h8: o3 = 7'b0000000;
				4'h9: o3 = 7'b0011000;
				4'hA: o3 = 7'b0001000;
				4'hB: o3 = 7'b0000011;
				4'hC: o3 = 7'b1000110;
				4'hD: o3 = 7'b0100001;
				4'hE: o3 = 7'b0000110;
				4'hF: o3 = 7'b0001110;
		endcase
	
	case(outA) 
				4'h0: o4 = 7'b1000000;
				4'h1: o4 = 7'b1111001;
				4'h2: o4 = 7'b0100100;
				4'h3: o4 = 7'b0110000;
				4'h4: o4 = 7'b0011001;
				4'h5: o4 = 7'b0010010;
				4'h6: o4 = 7'b0000010;
				4'h7: o4 = 7'b1111000;
				4'h8: o4 = 7'b0000000;
				4'h9: o4 = 7'b0011000;
				4'hA: o4 = 7'b0001000;
				4'hB: o4 = 7'b0000011;
				4'hC: o4 = 7'b1000110;
				4'hD: o4 = 7'b0100001;
				4'hE: o4 = 7'b0000110;
				4'hF: o4 = 7'b0001110;
		endcase
	end
	//------------------------------------------------------------------------------
	always @ (posedge clk) // displays the timer value
		begin
			if (count < 6'd10)
				begin 
					o6 <= 7'b1000000;
					case(count) // less than ten
						6'd0: o5 = 7'b1000000;
						6'd1: o5 = 7'b1111001;
						6'd2: o5 = 7'b0100100;
						6'd3: o5 = 7'b0110000;
						6'd4: o5 = 7'b0011001;
						6'd5: o5 = 7'b0010010;
						6'd6: o5 = 7'b0000010;
						6'd7: o5 = 7'b1111000;
						6'd8: o5 = 7'b0000000;
						6'd9: o5 = 7'b0011000;
					endcase
				end
			else if (count < 6'd20)// greater than or equal to ten
				begin
					o6 = 7'b1111001;
					case(count)
						6'd10: o5 = 7'b1000000;
						6'd11: o5 = 7'b1111001;
						6'd12: o5 = 7'b0100100;
						6'd13: o5 = 7'b0110000;
						6'd14: o5 = 7'b0011001;
						6'd15: o5 = 7'b0010010;
						6'd16: o5 = 7'b0000010;
						6'd17: o5 = 7'b1111000;
						6'd18: o5 = 7'b0000000;
						6'd19: o5 = 7'b0011000;
					endcase
				end
			else if (count < 6'd30)// greater than or equal to twenty
				begin
					o6 = 7'b0100100;
					case(count)
						6'd20: o5 = 7'b1000000;
						6'd21: o5 = 7'b1111001;
						6'd22: o5 = 7'b0100100;
						6'd23: o5 = 7'b0110000;
						6'd24: o5 = 7'b0011001;
						6'd25: o5 = 7'b0010010;
						6'd26: o5 = 7'b0000010;
						6'd27: o5 = 7'b1111000;
						6'd28: o5 = 7'b0000000;
						6'd29: o5 = 7'b0011000;
					endcase
				end
			else if (count < 6'd40)// greater than or equal to thirty
				begin
					o6 = 7'b0110000;
					case(count)
						6'd30: o5 = 7'b1000000;
						6'd31: o5 = 7'b1111001;
						6'd32: o5 = 7'b0100100;
						6'd33: o5 = 7'b0110000;
						6'd34: o5 = 7'b0011001;
						6'd35: o5 = 7'b0010010;
						6'd36: o5 = 7'b0000010;
						6'd37: o5 = 7'b1111000;
						6'd38: o5 = 7'b0000000;
						6'd39: o5 = 7'b0011000;
					endcase
				end
			else if (count < 6'd50)// greater than or equal to fourty
				begin
					o6 = 7'b0011001;
					case(count)
						6'd40: o5 = 7'b1000000;
						6'd41: o5 = 7'b1111001;
						6'd42: o5 = 7'b0100100;
						6'd43: o5 = 7'b0110000;
						6'd44: o5 = 7'b0011001;
						6'd45: o5 = 7'b0010010;
						6'd46: o5 = 7'b0000010;
						6'd47: o5 = 7'b1111000;
						6'd48: o5 = 7'b0000000;
						6'd49: o5 = 7'b0011000;
					endcase
				end
			else if (count < 6'd60)// greater than or equal to fifty
				begin
					o6 = 7'b0010010;
					case(count)
						6'd50: o5 = 7'b1000000;
						6'd51: o5 = 7'b1111001;
						6'd52: o5 = 7'b0100100;
						6'd53: o5 = 7'b0110000;
						6'd54: o5 = 7'b0011001;
						6'd55: o5 = 7'b0010010;
						6'd56: o5 = 7'b0000010;
						6'd57: o5 = 7'b1111000;
						6'd58: o5 = 7'b0000000;
						6'd59: o5 = 7'b0011000;
					endcase
				end
			else                //greater then or equal to sixty
				begin
					o6 = 7'b0000010;
					case (count)
						6'd60: o5 = 7'b1000000;
						6'd61: o5 = 7'b1111001;
						6'd62: o5 = 7'b0100100;
						6'd63: o5 = 7'b0110000;
					endcase
				end
		end
//--------------------------------------------------------------------------------------------------------------------
	endmodule
	